Packaged microelectronic devices are used in cellular phones, pagers, personal digital assistants, computers, and many other electronic products. Die-level packaged microelectronic devices typically include a die, an interposer substrate or leadframe attached to the die, and a molded casing around the die. The die generally has an integrated circuit and a plurality of bond-pads coupled to the integrated circuit. The bond-pads can be coupled to terminals on the interposer substrate or leadframe. The interposer substrate can also include ball-pads coupled to the terminals by conductive traces in a dielectric material. A plurality of solder balls can be attached to corresponding ball-pads to construct a “ball-grid” array. The steps for making die-level packaged microelectronic devices typically include (a) forming a plurality of dies on a semiconductor wafer, (b) cutting the wafer to singulate the dies, (c) attaching individual dies to corresponding interposer substrates, (d) wire-bonding the bond-pads to the terminals of the interposer substrate, and (e) encapsulating the dies with a molding compound.
Another process for packaging microelectronic devices is wafer-level packaging. In wafer-level packaging, a plurality of microelectronic dies are formed on a wafer and a redistribution layer is formed over the dies. The redistribution layer includes a dielectric layer, a plurality of ball-pad arrays on the dielectric layer, and a plurality of traces coupled to individual ball-pads of the ball-pad arrays. Each ball-pad array is arranged over a corresponding microelectronic die, and the traces couple the ball-pads in each array to corresponding bond-pads on the die. After forming the redistribution layer on the wafer, a stenciling machine can deposit discrete blocks of solder paste onto the ball-pads of the redistribution layer. The solder paste is then reflowed to form solder balls or solder bumps on the ball-pads. After forming the solder balls on the ball-pads, the wafer is cut to singulate the dies.
Another type of packaged microelectronic device is a build-up package (“BUP”) microelectronic device. BUP devices are formed by placing multiple singulated microelectronic dies active side down on a temporary carrier. A fill material is then used to cover the dies and the carrier. Once the fill material cures, the temporary carrier is removed. The active sides of the dies are cleaned, and then a redistribution layer is applied to the active sides. Solder balls can be connected to the redistribution layer, and a dielectric layer can be applied over portions of the redistribution layer so that the solder balls extend through the dielectric layer. The fill material between the dies is then cut to separate the dies from one another and form multiple BUP devices. The solder balls and redistribution layer can then be used to connect the BUP device to a printed circuit board.
BUP devices can also be formed by placing multiple singulated dies active side down on a temporary carrier, and placing fill material between the dies. Once the fill material hardens, the temporary carrier is removed and the BUP devices are separated by cutting the fill material between the dies. It may be difficult to place a redistribution layer on the active sides of the dies with this process, however, because the active sides and the fill material may not form a sufficiently planar surface for effective application of a redistribution layer, and the dies may be skewed such that precise wafer level processes cannot be used.
Whether the dies are encapsulated before or after dicing, the dies are generally organized in a rectilinear array of rows and columns that are separated by streets. The rows and columns are spaced apart from each other in a repeated pattern, generally with a fixed row spacing between neighboring rows, and a fixed column spacing between neighboring columns. The pattern is generally fixed for a given type of wafer and die configuration. Accordingly, even if a particular type of wafer has dies of different sizes, the dies are arranged in a predictable pattern that is repeated from one wafer to the next.
Prior to dicing, a camera or other type of imaging system is used to detect the rotational orientation of the array and the starting point at which the dicing process begins. A dicing blade is then brought into contact with the wafer and either the blade or the wafer is translated to make the first cut (e.g., along a column). The blade or the wafer is then stepped over to the next column by a known distance corresponding to the spacing between columns, and the next cut is made. This process is repeated until all the necessary column cuts are completed. At that point, the wafer (or the blade) is rotated 90° and the same process is repeated until all the row cuts are complete.
While the foregoing process has proven effective for many applications, in certain applications, the spacing between dies may not be consistent from one wafer to the next, or within a given wafer. In such a case, the rotating blade typically cannot account for spacing variations and as a result, may cut through dies that would otherwise be suitable for installation in an end product. Accordingly, there is a desire to improve the versatility of current singulation processes.
FIG. 1 is a schematic diagram of a prior art system 100 for imaging a semiconductor wafer 102 (“wafer 102”) and cutting the wafer 102 into individual dies. The system 100 includes an infrared camera 110 having an infrared detector array (not shown). The infrared camera 110 is operably coupled to a dicing machine 114 via a computer 112. The dicing machine 114 can include a saw having, for example, a diamond-tipped blade 116 that rotates about a spindle to cut through the wafer 102. The wafer 102 is supported by a chuck 104 that is operably coupled to a heat source 106. To facilitate cutting and/or imaging, the chuck 104 is able to move laterally in an X direction and rotate about its axis in a θ direction. Similarly, the dicing machine 114 is able to move up and down in a Y direction as well as back and forth in a Z direction.
In operation, the heat source 106 heats the wafer 102 to a predetermined temperature, causing the wafer 102 to generate infrared photons or “flux.” The detector array in the infrared camera 110 creates a map of the wafer 102 based on the flux intensity received by each of the individual detectors in the array. The computer 112 converts the flux detected by each of the detectors into a temperature reading corresponding to a feature on the wafer 102. This enables the computer 112 to determine the location of scribe lines and/or other alignment features (i.e., fiducials) on the wafer 102. The computer 112 provides this information to the dicing machine 114, which then cuts the wafer 102 along the scribe lines to singulate the individual dies.
Another type of infrared imaging system commonly used to align semiconductor wafers does not use a heat source to heat the wafer. This type of system is a reflective system that directs infrared radiation down onto the wafer, and then captures the infrared radiation that reflects off of the wafer with a camera that generates an image of the wafer.
Many semiconductor wafers include layers of material that can inhibit infrared imaging. For example, various types of memory and imaging semiconductor devices include metallized layers on the back side to enhance protection from electromagnetic interference (EMI). These metallized layers can obscure infrared radiation, making accurate infrared imaging difficult, if not impossible. In addition, when cutting BUP devices, the mold material can also obscure infrared imaging, again making it difficult to accurately detect the location of scribe lines and other alignment features. To overcome these problems, semiconductor wafers can be manufactured so that the metallized layer or mold compound is prevented from covering the alignment features. Alternatively, the infrared inhibiting material can be removed from around the alignment features prior to wafer imaging. Both of these approaches, however, are time consuming and can reduce the amount of space on a wafer available for producing dies. Therefore, it would be desirable to have a system for imaging and cutting semiconductor wafers that have infrared inhibiting layers obscuring alignment features.